Design and analysis of a high-performance CNFET-based Full Adder

This paper presents a high-speed and high-performance CNFET-based Full Adder cell for low-voltage applications. The proposed Full Adder cell is composed of two separate modules with identical hardware configurations which generate the Sum and Cout signals in a parallel manner. The great advantage of the proposed structure is its very short critical path which is composed of only two CNT pass-transistors. This design also takes advantage of the unique properties of MOSFET-like CNFETs such as the feasibility of adjusting the threshold voltage of a CNFET by adjusting the diameter of its nanotubes to correct the voltage levels as well as to achieve a high performance. Comprehensive experiments are performed in various situations to evaluate the performance of the proposed design. Simulations are carried out using Synopsys HSPICE with 32nm-CMOS and 32nm-CNFET technologies. The simulation results demonstrate the superiority of the proposed design in terms of speed, power consumption, power delay product (PDP) and less susceptibility to process variations, compared to other classical and modern CMOS and CNFET-based Full Adder cells.